Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size can be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
One common technique of interconnecting a semiconductor die with a printed circuit board or other device involves the use of solder bumps. FIG. 1 shows a conventional polyimide over UBM (POU) solder bump structure 10. An electrically conductive layer 14 is formed over an active surface of semiconductor wafer 12, and operates as a contact pad. Wafer 12 is inspected for initial quality control (IQC). An insulation or passivation layer 16 is formed over semiconductor wafer 12 and conductive layer 14. A portion of insulating layer 16 is removed by an etching process to expose a portion of conductive layer 14. Partially formed POU structure 10 undergoes a first scrubber clean. An electrically conductive layer or sputtered UBM 18 is formed over insulation layer 16 and conductive layer 14. A nickel (Ni) UBM or electrically conductive layer 20 is formed over and conformally applied to conductive layer 18 to operate as a bump pad for a later formed bump. Partially formed POU structure 10 undergoes a second scrubber clean. A layer of polyimide serves as an insulation or passivation layer 22, which is formed over conductive layer 18 and Ni UBM 20. The polyimide is coated, aligned, developed, cured, de-scumed, acid cleaned, and baked before dry film resist (DFR) laminating. An opening in insulation layer 22 is formed over Ni UBM 20. The DFR is laminated over insulation layer 22 and then undergoes an edge rinse, alignment, polyethylene terepthalate (PET) removal, development, first de-scum, hard bake, and second de-scum. Solder material is plated over of Ni UBM 20 and within an opening in the DFR layer. The DFR is stripped, plasma ash is applied, Ni UBM 20 is etched, and partially completed POU structure 10 undergoes a third scrubber clean. A flux coating is applied to the plated solder material, and the solder material is reflowed to form spherical ball or bump 24, which is formed over and electrically connects to Ni UBM 20. The device undergoes a flux clean, bump measurement, and final visual inspection (FVI) resulting in POU structure 10. Conventional POU structures like POU structure 10 include a risk of tin (Sn) from bump 24 traveling along a side wall of Ni UBM 20 to react with UBM copper (Cu) to form an inter metallic compound (IMC).
FIG. 2 shows a conventional polyimide and lead free bump structure 28. An electrically conductive layer 32 is formed over an active surface of semiconductor wafer 30 and operates as a contact pad. Wafer 30 is inspected for IQC. An insulation or passivation layer 34 is formed over semiconductor wafer 30 and contacts a sidewall of conductive layer 32. Partially formed bump structure 28 undergoes a scrubber clean and is baked. A layer of polyimide serves as an insulation or passivation layer 36, and is formed over conductive layer 32 and insulation layer 34. The polyimide is coated, aligned, developed, cured, de-scumed, and acid cleaned such that a portion of conductive layer 32 is exposed. An electrically conductive layer 38 is formed over and conformally applied to a portion of conductive layer 32 and a portion of insulation layer 36. In one embodiment, conductive layer 38 is sputtered to operate as a UBM for a later formed bump and includes one or more layers of titanium (Ti), Cu, and Ni. The device then undergoes a scrubber clean, and a DFR layer is laminated over insulation layer 36 and conductive layer 38. The DFR layer undergoes an edge beam rinse, alignment, PET removal, development, first de-scum, hard bake, and second de-scum. Solder material is plated over conductive layer 38 and within an opening in the DFR layer. The DFR is stripped, conductive layer 38 is etched, and the device undergoes a third scrubber clean, a first nitrogen gas (N2) treatment, a second etching, a fourth scrubber clean, a hard bake, and an oxygen gas (O2) plasma treatment. A flux coating is applied to the plated solder material, and the solder material is reflowed to form spherical ball or bump 40, which is formed over and electrically connects to conductive layer 38. The device then undergoes a flux clean, a second N2 treatment, bump measurement, a fifth scrubber clean, and FVI resulting in the polyimide and lead free bump structure 28.
Concerns regarding the reliability of solder joints are more acute for flipchip bonding with lead free solder, such as those presented in FIGS. 1 and 2. Lead free solders include Sn-based alloys with Cu and silver (Ag) which have higher melting points than traditional eutectic SnPb solders. The higher temperatures and higher Sn concentrations lead to more severe reactions between the SnPb solders and the UBMs which can lead to excessive IMC formation that may cause dewetting on the UBM and result in weak solder joints.